library IEEE;
use IEEE.std_logic_1164.all;
entity ARST is
port (
CLK: in STD_LOGIC;
RSTO: out STD_LOGIC
);
end ARST;
architecture ARST_arch of ARST is
signal CNTDYN: INTEGER range 0 to 255;
begin
process (CLK) begin
if(CLK = '1' and CLK'event) then
if(CNTDYN = 128) then
RSTO <= '0';
else
CNTDYN <= CNTDYN + 1;
RSTO <= '1';
end if;
end if;
end process;
end ARST_arch;
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